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5
5 - 118
Truth Table
Control Voltage
Bias Voltage & Current
Worst Case Step Error
Between Successive Attenuation States
Vdd Range = 3.0 to +5.0 Vdc
Vdd
(VDC)
Idd (Typ.)
(糀)
+3.0
10
+5.0
30
State
Bias Condition
Low
0 to 0.2V @ 10 uA Typ.
High
Vdd ?0.2V @ 5 uA Typ.
Note: Vdd = +3V to +5V
Control Voltage Input
Attenua-
tion State
RF1 - RF2
V1
16 dB
V2
8 dB
V3
4 dB
V4
2 dB
V5
1 dB
V6
0.5 dB
High
High
High
High    High
High
Reference
I.L.
High
High
High
High    High
Low
0.5 dB
High
High
High
High
Low
High
1 dB
High
High
High
Low
High
High
2 dB
High
High
Low
High    High
High
4 dB
High
Low
High
High    High
High
8 dB
Low
High
High
High    High
High
16 dB
Low
Low
Low
Low
Low
Low
31.5 dB
Any combination of the above states will provide an attenuation
approximately equal to the sum of the bits selected.
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
HMC425LP3 / 425LP3E
v03.0409
0.5 dB LSB GaAs MMIC 6-BIT DIGITAL
POSITIVE CONTROL ATTENUATOR, 2.2 - 8.0 GHz
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